1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, particularly, to a large scale semiconductor integrated circuit (LSI) containing a substrate biasing voltage generator circuit for applying a reverse biasing voltage to a semiconductor substrate formed on its surface with an internal circuit and a voltage drop circuit for dropping an external power source voltage to obtain an internal source voltage to be supplied to the substrate biasing voltage generator circuit and the internal circuit as operating voltages thereof.
2. Description of the Prior Art
It is usual that, in order to increase an operating speed of an LSI and improve a stability thereof, the LSI contains a substrate biasing voltage generator circuit for applying a reverse biasing voltage (substrate biasing voltage) to a substrate formed on its surface with an internal circuit to reduce junction capacitance between the substrate and source/drain regions of MOS transistors constituting the internal circuit and to reduce the dependency of threshold voltages of the MOS transistors on the substrate biasing voltage. The substrate biasing voltage generator circuit has to be capable of minimizing undesired effects of existence thereof such as an increase of power consumption of the LSI and an operational delay of the LSI, specifically, an increase of time period from a time when an external power source voltage is applied thereto for which the LSI becomes in a ready state in which it is responsible to an external start control signal. A technique satisfying these requirements are disclosed in Japanese Kokai (P) No. Sho 61-95561.
An LSI disclosed in the Kokai contains two substrate biasing voltage generator circuit portions connected in parallel to each other between an output terminal of a substrate and a ground line of an internal circuit formed on the substrate and having different substrate current absorbing capabilities, that is, capabilities to allow substrate current caused by electric charge leaked from current in MOS transistors constituting the internal circuit to the substrate to be discharged to the ground line. The LSI further includes a control signal generator circuit for determining whether the substrate biasing voltage is increased to a predetermined voltage when an external power source voltage is applied thereto.
Since one of the substrate biasing voltage generator circuit portions, that is, one to be used in a standby model is enough to absorb a small substrate current corresponding to a standby current in the LSI in the standby mode, that is, a total current flowing from the external power source to the LSI in the standby state, its substrate current absorbing capability is small and thus its power consumption is small. On the other hand, since the other substrate biasing voltage generator circuit must absorb a large substrate current corresponding to an operating current of the LSI in an active mode, that is, a total current flowing from the external power source circuit to the LSI in the active mode, its substrate current absorbing capability is large and hence its power consumption is large.
During a time period in which an applied external power source voltage is in a normal level and the LSI is operating therewith, the substrate biasing voltage generator circuit portions operate to maintain the substrate biasing voltage at a predetermined voltage value, respectively. In detail, during a time period immediately after the external power source voltage is applied to the LSI and before the LSI is still in a state in which it can respond to any external input signal as yet, the active mode substrate biasing voltage generator circuit portion operates to rapidly increase the substrate biasing voltage to the predetermined voltage value by means of its large substrate current absorbing capability to thereby accelerate a start of operation of the LSI. That is, at the time when the external power source voltage is applied to the LSI, the control signal generator circuit first activates the active mode substrate biasing voltage generator circuit portion. Thereafter, when the control signal generator circuit detects the substrate biasing voltage reached the predetermined voltage value, it decides the LSI as to be operable and generates a control signal for starting the operation of the LSI. The control signal also makes the active mode substrate biasing voltage generator circuit portion switchable to the standby mode substrate biasing voltage generator circuit portion of small power consumption so that the substrate biasing voltage can be maintained constant.
The substrate biasing voltage generator circuit portions having different substrate current absorbing capabilities are used alternatively as mentioned above depending upon the operation mode of the LSI. That is, the active mode substrate biasing voltage generator circuit portion having large power consumption operates to absorb the substrate current only in the short time after the external power source voltage is applied to the LSI to thereby accelerate the rise of the substrate biasing voltage and in the active mode operation time of the LSI with the normal level external power source voltage to increase the operating speed of the LSI, while restricting a total power consumption of the whole LSI.
Besides, due to increased capacity of an LSI, there is a tendency that the LSI contains a voltage drop circuit for dropping an external power source voltage to an internal power source voltage and supplying the latter to the internal circuit thereof. When the technique disclosed in the aforementioned Kakai (P) Sho 61-95561 is to be applied to an LSI having such voltage drop circuit, the rising rate of the substrate biasing voltage after the external power source voltage is applied to the LSI is reduced, causing the start of operation of the LSI to be delayed. In order to avoid such delay, power consumption of a whole chip may be substantially increased. In an LSI in which a substrate biasing voltage generator is operated with the internal power source voltage from the voltage drop circuit, it is very difficult to reconcile acceleration of the start of operation of the LSI when the application of the external power source voltage and reduction of power consumption during a normal operation thereof.
In order to reduce power consumption of an LSI having a substrate biasing voltage generator circuit and a voltage drop circuit, a substrate biasing voltage generator circuit must be operated by an internal power source voltage. For example, it is assumed that a 16M bit DRAM operable with an internal power source voltage of 3.3 V obtained by dropping an external power source voltage of 5 V, and with a substrate biasing voltage being in the order of -2.0 V. When a standby mode substrate biasing voltage generator circuit portion is operated with the internal power source voltage of 3.3 V, a standby current including current to be consumed by the substrate biasing voltage generator circuit portion itself may be 300 .mu.A at most. However, when it is operated with the external power source voltage of 5 V, the standby current is substantially increased up to the order of 7 to 8 mA a major part of which is consumed by the substrate biasing voltage generator circuit portion. On the other hand, when the substrate biasing voltage generator circuit portion is operated with the internal power source voltage from the voltage drop circuit, the power consumption of the whole chip can be restricted to a small value. However, the acceleration effect of the start of operation of the LSI at the time of application of the external power source voltage is lost.
The voltage drop circuit included in the LSI operates to drop the external power source voltage by a control signal generated within the chip after the external power source voltage is applied. Further, a parasitic capacitance of the internal power source line which may be provided mainly by junction capacitance in source/drain regions of MOS transistors constituting the internal circuit must be charged by an output voltage of the voltage drop circuit. Therefore, delay including time necessary to rise of the external power source voltage to a sufficient level in the chip, time necessary to generate the control signal to drop the external power source voltage to the internal power source voltage and time necessary to charge the parasitic capacitance is unavoidable. Thus, in the LSI including the substrate biasing voltage generator circuit driven by the internal power source voltage whose rising rate is lowered, a rising rate of the substrate biasing voltage is also lowered. Since the LSI disclosed in Kokai starts to operate according to the control signal generated by the control signal generator circuit upon detection of the substrate biasing voltage reached the predetermined value, the start of operation thereof is delayed.
One of methods for reducing power consumption of a whole LSI by operating the substrate biasing voltage generator circuit with the internal power source voltage while preventing the above mentioned delay of start of LSI operation is to use of a power-on circuit instead of such control signal generator circuit as used in the LSI disclosed in Kokai. A power-on circuit generally functions to monitor rising rate of the external power source voltage in a LSI, to inhibit input of an external start control signal (for example, RAS signal in DRAM) to the LSI to thereby prevent the internal circuit of the LSI from entering into an operating state until the external power source voltage reaches a predetermined voltage value and to generate a control signal for allowing the control signal to be input when the external power source voltage exceeds the predetermined voltage value to thereby make the LSI in operable state. By using the control signal from the power-on circuit instead of the control signal from the control signal generator circuit of the Kokai, the timing at which the LSI becomes operable after application of external power source voltage is controlled by the rising rate of not the substrate biasing voltage but the external power source voltage. Therefore, there is no case where the start of operation of the LSI is delayed by delay in operation of the voltage divider circuit, that is, lowered rising rate of the internal power source voltage.
In the LSI having the power-on circuit, the latter does monitor not the internal power source voltage or the substrate biasing voltage itself which is a reflection of rising rate of the internal power source voltage but the external power source voltage. Therefore, when there is a large difference in rising rate between the external power source voltage and the internal power source voltage, the substrate biasing voltage may not reach a predetermined voltage value due to lowered rising rate of the internal power source voltage even when the external power source voltage has reached the predetermined voltage value and so the LSI has started its operation.
In such case, the LSI may start to operate although a threshold voltage of a MOS transistor which may be in the order of the second power of the substrate biasing voltage does not reach the predetermined voltage value as yet. Therefore, both the standby current in the standby mode and the operating current in the active mode are increased beyond predetermined values. Since the standby mode substrate biasing voltage generator circuit portion and the active mode substrate biasing voltage generator circuit portion do not have capabilities of absorbing the substrate current increased to such level, the substrate biasing voltage after the LSI starts to operate is restricted to the voltage value at the start of operation of the LSI and therefore the threshold voltage of the MOS transistor never reaches the predetermined voltage value. As a result, the LSI operates with large current even after start of its operation regardless of operation mode and thus power consumption of the LSI is increased and malfunction may occur.